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A.     Journal papers (Publications Top Page)

  1. K.-J. Lee, Z.-W. Lu and S.-J. Yeh, A Secure JTAG Wrapper for SoC Testing and Debugging, vol. 10, pp. 37603-37612, IEEE Access, 2022.

  2. K.-J. Lee, C.-A. Liu and C.-C. Wu, “A Dynamic Key Based Secure Scan Structure for Manufacturing and In-Field IC Testing,” IEEE Trans. Emerging Topics in Computing, vol. 10, no. 1, pp. 373-385, Mar. 2022.

  3. K.-J. Lee, C.-H. Wu, and T.-Y. Hou, “An efficient procedure to generate highly compact diagnosis patterns for transition faults,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Early access available in IEL, 2021.

  4. C.-S. Ye, S.-X. Zheng F.-J. Tsai, C. Wang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, J. Zawada, M. Kassab, J. Rajski, “Efficient Test Compression Configuration Selection,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Early access available in IEL, 2021.

  5. Y.-H. Chen, C.-M. Hsu, and K.-J. Lee, “Test Chips with Scan-Based Logic Arrays,” IEEE Trans. Very Large Scale Integration Systems, vol. 40, no. 4, pp. 790-802, Apr. 2021.

  6. Y.-C. Kung, K.-J. Lee, and S. M. Reddy, “Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6. pp. 1340-1345, June 2020.

  7. C.-H. Wu, K.-J. Lee, S. M. Reddy, “An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test-Compaction,” IEEE Trans. Very Large Scale Integration Systems. vol. 27, no. 9, pp. 2105~2118, 2019.

  8. K.-J. Lee, B.-R. Chen, and M. A. Kochte, “On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Scan Chains,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.38, no. 2, pp. 309-321, Feb., 2019.

  9. C.-H. Wu, S.-L. Lin, K.-J. Lee and S.M. Reddy, “A Repair-for-Diagnosis Methodology for Logic Circuits,” IEEE Transactions on Very Large Scale Integration Systems, vol.26, no.11, pp. 2254-2267, Nov., 2018.

  10. C.-W. Wu, K.-J. Lee, and A. P. Su, “A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip,” IEEE Trans. Computers, vol. 67, no. 9, pp. 1231-1245, Sep., 2018.

  11. J.-Z. Chen and K.-J. Lee, “Test Stimulus Compression Based on Broadcast Scan with One Single Input,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp. 184-197, Jan. 2017.

  12. W.-H. Hsu, M. A. Kochte, and K.-J. Lee, “Built-In Test and Diagnosis for TSVs with Different Placement Topologies and Crosstalk Impact Ranges,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 6, pp. 1004-1017, June 2017.

  13. K.-K. Liu, W.-H Hsu, and K.-J. Lee, “A high-performance SoC debug platform,” Smart Science, vol 3, no 4, pp. 202-208, 2015.

  14. W.-C Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh, “Efficient LFSR reseeding based on internal-response feedback,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 30, no. 6, pp. 673-685, Dec. 2014.

  15. C.-Y. Chang and K.-J. Lee, “On deadlock problem of on-chip buses supporting out-of-order transactions,” IEEE Trans. Very Large Scale Integration Systems. vol. 22, no. 3, pp. 484-496, Mar. 2014.

  16. Y.-H. Li, W.-C. Lien, I.-C. Lin, and K.-J. Lee, “Capture-power-safe test pattern determination for at-speed scan-based testing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 127-138, Jan. 2014.

  17. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and W.-L. Ang, “An efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 8, pp. 1254-1264, August, 2013.

  18. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty, and Y.-H. Wu, “Counter-based output selection for test response compaction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 1, pp. 152~164, Jan., 2013.

  19. K.-J. Lee, T.-Y. Hsieh, and M. A. Breuer, “Efficient over-detection elimination of acceptable faults for yield improvement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 5, pp. 754-764, May, 2012.

  20. K.-J. Lee, W.-C. Lien, and T.-Y. Hsieh, “Test response compaction via output bit selection,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 10, pp. 1534-1544, Oct. 2011.

  21. T.-Y. Hsieh, K.-J. Lee, and M. A. Breuer, “An error-tolerance-based test methodology to support product grading for yield enhancement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 6, pp. 930-934, Jun. 2011.

  22. C.-M. Huang, C.-M. Wu, C.-C. Yang, S.-L. Chen, C.-S. Chen, J.-J. Wang, K.-J. Lee, and C.-L. Wey, “Programmable system-on-chip (SOC) for silicon prototyping,” IEEE Trans. Industrial Electronics, 58(3), 830-838, 2011.

  23. K.-J. Lee, T.-Y. Hsieh, and C.-Y. Chang, “On-chip SOC test platform design based on IEEE 1500 Standard,” IEEE Trans. Very Large Scale Integration Systems, vol. 18, no. 7, 1134-1139, July, 2010.

  24. T.-H. Lu, C.-H. Chen, and K.-J. Lee, “Effective hybrid test program development for software-based self-testing of pipeline processor
    cores,” IEEE Trans. Very Large Scale Integration Systems, vol. 19, no. 3, pp. 516-520, March 2009.

  25. L.-T. Wang, R. Apte, S. Wu, B. Sheu, K.-J. Lee, X. Wen, W.-B. Jone, W.-S. Wang, H.-J. Chao, J. Guo, J. Liu, Y. Niu, Y.-C. Sung, C.-C. Wang, and F. Li, “Turbo1500: Core-based design for test and diagnosis using the IEEE 1500 Standard,” IEEE Design & Test of Computers, vol. 26, no. 1, pp. 26-35, 2009.

  26. T.-Y. Shieh, K.-J. Lee, and M.A. Breuer, “An error-rate based test methodology to support error-tolerance,” IEEE Trans. Reliability, vol. 57, no. 1, pp. 204-214, Jan, 2008.

  27. K.-J. Lee, C.-M. Huang, C.-C. Yang, C.-M. Wu, and J.-Y. Jou, “Multi-project system-on-chip (MP-SoC): a novel cost-efficient silicon prototyping service for academic soc designs,” Innovations 2007: World Innovations in Engineering Education and Research, pp. 391-400, 2007.

  28. W.-C. Huang, K.-J. Lee, C.-Y. Chang, and Y.-H. Wu, “DASTEP: A design automation system for SOC test platform,” Int’l Journal on Electrical Engineering, vol.14, no. 3, pp. 219-227, June 2007. (EI)

  29. T.-Y. Shieh, K.-J. Lee, and M.A. Breuer, “Preventing over-detection of acceptable faults for yield enhancement,” Int’l Journal on Electrical Engineering, vol. 14, no. 3, pp. 185-193, June 2007.(EI)

  30. T.-C. Huang and K.-J. Lee, “A hybrid LFSR design for low power applications,” Journal of Chinese Institute of Electrical Engineering, vol. 10, no. 1, pp. 1-8, Feb. 2003. (EI)

  31. J.-J. Chen, J.-K. Yung, and K.-J. Lee, “Test pattern generation & clock disabling for simultaneous test time and power reduction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 3, pp. 363-370, Mar., 2003.

  32. W.-B. Jone, D.-C. Huang, S.C. Wu, and K.-J. Lee, “An efficient BIST method for small buffers,” IEEE Trans. Very Large Scale Integration Systems, vol. 10, no. 4, pp. 512-515, Aug., 2002.

  33. T.-C. Huang and K.-J. Lee, “An interleaving technique for reducing peak power in multiple chain scan circuits during test application,” Journal of Electronic Testing, Theory and Applications (JETTA), vol.18, no.6, pp. 627-636, Dec. 2002.

  34. W.-L. Wang and K.-J. Lee, “An efficient deterministic test pattern generator for scan-based bist environment,” Journal of Electronic Testing, Theory and Applications (JETTA), vol.18, no.1, pp. 43-53, Feb. 2002.

  35. Y.-C. Wen and K.-J. Lee, “A current-mode BIST structure of DACs,” Journal of the Int’l Measurement Confederation (IMEKO), Measurement 31, pp. 147-163, 2002.

  36. K.-J. Lee and W.-C. Wang, “A 0.5μm concurrent testable chip of a fifth-order gm-C filter,” Analog Integrated Circuits and Signal Processing, vol. 32, pp. 231-247, 2002.

  37. W.-L. Wang and K.-J. Lee, “An on-chip March pattern generator for testing embedded memory cores,” IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 5, pp. 730-735, Oct. 2001.

  38. K.-J. Lee and C.-I Huang, “A hierarchical test control architecture for SOC design,” Journal of Chinese Institute of Electrical Engineering, vol. 8, no. 4., pp. 355-364, 2001.

  39. W.-L. Wang and K.-J. Lee, “Fast deterministic test pattern generation for scan-based BIST environment,” Journal of Chinese Institute of Electrical Engineering, vol. 8, no. 4., pp. 365-376, 2001.

  40. K.-J. Lee and T.-C. Huang, “Reduction of power consumption in scan-based circuits during test application by an input control technique,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 911-917, July, 2001.

  41. T.-C. Huang and K.-J. Lee, “Token scan cell for low power testing,” IEE Electronics Letters, vol.37, no.11, pp. 678-679, May 2001.

  42. Y.-C. Wen and K.-J. Lee, “Analysis and generation of control and observation structures for analog circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.20, no.1, pp. 165-171, Jan., 2001.

  43. S.C. Chang, K.-J. Lee, Z.-Z. Wu, and W.-B. Jone, “Reducing test application time by scan flip-flops sharing,” IEE Proceedings on Computers and Digital Technology, vol. 147, pp. 42-52, Jan. 2000.

  44. K.-J. Lee, “On the testing of semiconductor memory,” Engineering Science & Technology Bulletin of NSC, no. 43, pp. 38-41, Jan. 2000.

  45. K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Broadcasting test patterns to multiple circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.18, no.12, pp. 1793-1802, Dec. 1999.

  46. K.-J. Lee, W.-C. Wang, and K.-S. Huang, “A current-mode testable design of OTA-C filters,” IEEE Trans. Circuits and Systems, Part II, vol.46, no.4, pp. 401-413, April, 1999.

  47. K.-J. Lee, J.-J. Tang, and T.-C. Huang, “BIFEST: An intermediate fault effect sensing and test generation system for CMOS bridging faults,” ACM Trans. Design Automation of Electronic Systems, pp. 194-218, Apr. 1999.

  48. K.-J. Lee and C.-H. Kuo, “Concurrent error detection, diagnosis, and fault tolerance for switched-capacitor filters,” Journal of Information Science and Engineering, vol.14, no.4, pp. 863-890, Dec. 1998.

  49. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A graph representation for PLA to facilitate testing and logic design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.17, no.10, pp. 1030-1043, Oct. 1998.

  50. K.-J. Lee, W.-L. Wang, and J.-F. Wang, “A general structure of feedback shift registers for built-in self-test,” Journal of Information Science and Engineering, vol.14, no.3, pp. 645-667, Sep. 1998.

  51. Y.-C. Wen and K.-J. Lee, “BIST structure for DAC testing,” IEE Electronics Letters, vol.34, no.12, pp..1173-1174, Jun. 1998.

  52. K.-J. Lee and J.-J. Tang, “A built-in current sensor based on current-mode design,” IEEE Trans. Circuits & Systems, Part II, vol.45, no.1, pp. 133-137, Jan. 1998.

  53. K.-J. Lee and Y.-C. Wen, “Two novel control and observation structures for Analog circuits,” IEE Electronics Letters, vol.33, no.19, pp..1590-1592, Sep. 1997.

  54. K.-J. Lee, K.-S. Huang, and W.-C. Wang, “A concurrent test method for OTA-C filters,” IEE Electronics Letters, vol.33, no.1, pp. 1-2, Jan. 1997.

  55. K.-J. Lee, K.-S. Huang, and M.-C. Huang, “Design of low voltage built-in current sensors,” IEE Electronics Letters, vol.32, no.21, pp. 1942-1943, Oct. 1996.

  56. K.-J. Lee, “IDDQ testing: a new IC testing method (Invited),” Electronic Magazine, no.16, pp. 60-65, Nov. 1996.

  57. K.-J. Lee, T.-P. Lee, R.-C. Wen, and Z.-Y. Lin, “Analogue boundary scan architecture for DC and AC testing,” IEE Electronics Letters, vol.32, no.8, pp. 704-705, Apr.11, 1996.

  58. K.-J. Lee, C.-N. Wang, R. Gupta, and M.A. Breuer, “An integrated system for assigning signal flow directions to CMOS transistors,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.14, no.12, pp. 1445-1458, Dec. 1995.

  59. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A practical current sensing technique for IDDQ testing,” IEEE Trans. Very Large Scale Integration Systems, vol.3, no.2, pp. 302-310, June, 1995.

  60. K.-J. Lee, C.A. Njinda, and M.A. Breuer, “SWiTEST: A switch level test generation system for CMOS combinational circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.13, no.5, pp. 625-637, May 1994.

  61. K.-J. Lee and M.A. Breuer, “Design & test rules for CMOS circuits to facilitate IDDQ testing to detect bridging faults,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.11, no.5, pp. 659--670, May 1992.


B.     Conference/Symposium/Workshop  (Publications Top Page)

 

 

  1.  S.-X. Zheng, C.-Y. Yeh, K.-J. Lee, C. Wang, W.-T. Cheng, M. Kassab, J. Rajski, S. M. Reddy, “Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations,” VLSI Test Symposium, 2022.

  2. H.-Y. Chi and K.-J. Lee, “Lightweight  Hardware-Based Memory Protection Mechanism on IoT Processors,” IEEE Asian Test Symp., 2021, Accepted.

  3. S.-X. Zheng, C.-S. Ye, K.-J. Lee, “Pattern Count Estimation and Optimum Configuration Selection for Test Compression Configurations in Scan-Based Design,” VLSI Test Technology Workshop, 2021, Best paper award.

  4. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.X. Zheng, “Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channels Configurations,” accepted, IEEE International Test Conference (ITC), 2020.

  5. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.X. Zheng, “Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels,” accepted, IEEE International Test Conference in Asia (ITC-Asia), 2020.

  6. K.-J. Lee, et al., High Security and Low Power Integrated Circuits and Systems for IoT Design and Analysis, VLSI DESIGN/CAD Symp, 2020.

  7. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, S.-X. Zheng, “Prediction of Test Data Volume for Scan Architectures with Different Input Commpression Ratio,” accepted, VLSI Test Technology Workshop, 2020.

  8. F.-J. Tsai, C.-S. Ye, Y. Huang, K.-J. Lee, W.-T. Cheng, S. M. Reddy, M. Kassab, J. Rajski, “Efficient Prognostication of Pattern Count with Different Input Compression Ratios,” accepted, European Test Symp., 2020.

  9. C-H. Wu, Y. Huang, K.-J. Lee, W.-T. Cheng, G. Veda, S. M. Reddy, C.-C. Hu, C.-S. Ye, “Deep learning based test compression analyzer,” accepted, Asian Test Symp. 2019.

  10. M.-H. Kuo and K.-J. Lee, “Time-Related Hardware Trojan Attacks on Processor Cores,” accepted, Intl’ Test Conf. in Asia, 2019.

  11. M.-H. Kuo and K.-J. Lee, “Designing Time-Based Hardware Trojans,” accepted, VLSI Test Technology Workshop, 2019.

  12. C.-J. Shang, C.-H. Wu, K.-J. Lee, and Y.-H. Chen, “A Novel Test Generation Method for Small Delay Defects with User-Defined Fault Model,”, IEEE Int’l VLSI Symp. on Design, Automation and Test, 2019.

  13. Y.-C. Kung, K.-J. Lee, S. M. Reddy, “Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run, IEEE International Test Conference (ITC), pp. 1-10, 2018.

  14. C.-C. Wu, M.-H. Kou, K.-J. Lee, “A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks,” IEEE Asian Test Symposium (ATS), pp. 48-53, 2018.

  15. Y.-C. Kung, K.-J. Lee, and S. M. Reddy, “Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run,”IEEE International Test Conference in Asia (ITC-Asia), pp. 1-6, 2018.

  16. Y.-C. Kung, K.-J. Lee and S.M. Reddy, “Compact Test Pattern Generation for Stuck-at Faults and Transition Faults,” in Proc., VLSI Test Technology Workshop, 2018.

  17. C.-W. Chen, Y.-C. Kong and K.-J. Lee, “Test Compression with Single-Input Data Spreader and Multiple Test Sessions,” accepted, Asia Test Symposium, 2017.

  18. S.-L. Hong and K.-J. Lee, “A Run-Pause-Resume Silicon Debug Technique for Multiple Clock Domain Systems,” IEEE Int’l Test Conference in Asia, Paper B2.3, 2017.

  19. C.-H. Wu, K.-J. Lee and S. M. Reddy, “Test Generation for Open and Delay Faults in CMOS Circuits,” IEEE Int’l Test Conference in Asia, Paper C1-2, 2017.

  20. K.-J. Lee, P.-H. Tang, M. A. Kochte and B.-R. Chen, “An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains, VLSI DESIGN/CAD Symp, 2017.

  21. S.-L. Hong and K.-J. Lee, “A Silicon Debug Technique for Multiple Clock Domain Systems,” VLSI Test Technology Workshop, Paper S1-2, 2017.

  22. H.-P. Kuo, A. P. Su and K.-J. Lee, “A Low Power Synthesis Flow for Multi-Rate Systems,” accepted, IEEE Int’l VLSI Symp. on Design, Automation and Test, 2017.

  23. J.-C. Ye, M. A. Kochte, K.-J. Lee, and H-J. Wunderlich, “Autonomous Testing for 3D-ICs with IEEE Std. 1687,” accepted, IEEE Asian Test Symposium, 2016

  24. S.-L. Lin, C.-H. Wu, K.-J. Lee, “Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis,” accepted, IEEE Asia Test Symposium, 2016

  25. W.-C. Lien and K.-J. Lee, “Output Bit Selection Methodology for Test Response Compaction,” Paper TC.2, IEEE Int’l Test Conf., 2016

  26. C. H. Wu, S. J. Lee and K. J. Lee, "Test and diagnosis pattern generation for dynamic bridging faults and transition delay faults,"  Asia and South Pacific Design Automation Conference , 2016

  27. C. M. Shiao, W. C. Lien and K. J. Lee, "A Test-per-cycle BIST architecture with low area overhead and no storage requirement,"  International Symposium on VLSI Design, Automation and Test, 2016

  28. K.-J. Lee, P.-H. Tang and M. A. Kochte, “An On-Chip Self-Test Architecture with Test Patterns Recorded in Scan Chains,” Paper 16.3, IEEE Int’l Test Conf., 2016

  29. C.-H. Wu, K.-J. Lee, “Transformation of Multiple Fault Models to a Unified Model for ATPG Efficiency Enhancement,” Paper 16.1, IEEE Int’l Test Conf., 2016

  30. J.-C. Ye, M. A. Kochte, K.-J. Lee, and H-J. Wunderlich, “A High-Efficiency 3D-IC Test Architecture with IEEE Std. 1687, Post-E, VLSI DESIGN/CAD Symp., 2016

  31. C.-H. Wu, K.-J. Lee, “An Efficient Test Pattern Generation Method for Cell-Internal Faults,” VLSI DESIGN/CAD Symp., Paper S5-2, 2016. (Best paper award)

  32. S.-L. Lin, C.-H. Wu, K.-J. Lee, “Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault Diagnosis,” VLSI Test Technology Workshop, 2016

  33. W.-H. Hsu, M. A. Kochte, and K.-J. Lee, “3D-IC Test Architecture for TSVs with Different Impact Ranges of Crosstalk Faults,” IEEE Int’l VLSI Symp. on Design, Automation and Test, 2016

  34. J.-C. Ye, M. A. Kochte, K.-J. Lee, and H-J. Wunderlich, “Autonomous Testing for 3D-ICs with IEEE Std. 1687,” International Test Standards Application Workshop, 2016

  35. L.-Y. Lu, C.-Y. Chen, Z.-H. Chen, B.-T. Yeh, T.-H. Lu, P.-Y. Chen, P. H. Tang, K.-J. Lee, L.-Y. Chiou, S.-J. Chang, C.-H. Tsai, C.-H. Chen, and J.-M. Lin, “A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling,”IEEE Asia and South Pacific Design Automation Conference, 2016.

  36. C.-H. Wu, S. J. Lee and K.-J. Lee, “Test and Diagnosis Pattern Generation for Dynamic Bridging Faults and Transition Delay Faults,” accepted, IEEE Asia and South Pacific Design Automation Conference, 2016.

  37. C.-H. Wu, S. J. Lee and K.-J. Lee, “Distinguishing Dynamic Bridging Faults and Transition Delay Faults,” accepted, IEEE Int’l Conf. on ASIC.

  38. C.-M. Shiao, W.-C. Lien and K.-J. Lee, “A Circular BIST Architecture using Internal Responses of Circuits for Reseeding and Extra Observation,” IEEE Workshop on RTL and High Level Testing (WRTLT), 2015, pp. 60-65. (Best Paper Award)

  39. C.-H. Wu, K.-J. Lee, and S.-T. Wang, “Diagnosis pattern generation for inter-gate and intra-gate faults in CMOS circuits,” VLSI DESIGN/CAD Symp., Paper S14-1, 2015.

  40. C.-H. Wu, K.-J. Lee, “An efficient diagnosis pattern generation method for stuck-at-faults with high test compaction,” VLSI DESIGN/CAD Symp., Paper S02-5, 2015. (Best paper award)

  41. C.-H. Wu, K.-J. Lee, and S.-T. Wang, “Diagnosis pattern generation to distinguish transition delay faults and transistor stuck-open faults,” VLSI Test Technology Workshop, Paper S1.1, 2015 (Best paper award).

  42. C.-H. Wu, and K.-J. Lee, “Improve Transition Fault Diagnosability Via Observation Point Insertion,” IEEE Int’l VLSI Symp. on Design, Automation and Test, 2015.

  43. H.-C. Chen, C.-R. Wu, K. S.-M. Li, and K.-J. Lee, “A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC,” IEEE Design, Automation and Test in Europe, pp. 1281-1284, 2015.

  44. L.-C. Li, W.-H. Hsu, K.-J. Lee and C.-L. Hsu, “An efficient 3D IC test framework to embed TSV testing in memory BIST,” IEEE Asia and South Pacific Design Automation Conference, pp.520-525, 2015.

  45. Y.-D. Wang, and K.-J. Lee, “Efficient Diagnosis Pattern Generation for Transition Faults Using Combinational Circuit Model,” IEEE Workshop of Register-Transfer and High Level Testing, pp. I.4.S, 2014.

  46. C.-H. Wu, and K.-J. Lee, “An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults,” IEEE Asian Test Symp. pp. 306-311,, 2014.

  47. Y.-D. Wang, and K.-J. Lee, “Efficient Diagnosis Pattern Generation for Transition Faults Using Combinational Circuit Model,” invited paper, IEEE Int’l Conf. Solid-State Integrated Circuit Technology, 2014.

  48. K.-J. Lee and C.-H. Wu, “An Efficient Diagnosis-Aware Pattern Generation Procedure for Transition Faults,” IEEE Int’l Test Conf., 2014.

  49. W.-C. Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh, “Output-Bit Selection with X-Avoidance using Multiple Counters for Test-Response Compaction, IEEE European Test Symp., May 2014.

  50. W.-C. Lien, K.-J. Lee, K. Chakrabarty, and T.-Y. Hsieh, “Output Selection for Test Response Compaction Based on Multiple Counters,” IEEE Int’l VLSI Symp. on Design, Automation and Test., pp. DR112, Apr. 2014.

  51. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit model,” IEEE VLSI Test Symp., pp. 240-245, 2014.

  52. W.-C. Lien, K.-J. Lee, K. Chakrabarty, T.-Y. Hsieh, and C.-H. Wu, “Compression of test response with many unknown values using multiple counters,” VLSI DESIGN/CAD Symp., Paper S15-4, 2014.

  53. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient stuck-at-fault diagnosis model using a single circuit model,” VLSI DESIGN/CAD Symp., Paper S15-1, 2014.

  54. C.-H. Wu, K.-J. Lee, and W.-C. Lien, “An efficient diagnosis pattern generation procedure,” VLSI Test Technology Workshop, Paper S1.1, 2014.

  55. H.-C. Chen, K. S.-M. Li, and K.-J. Lee, “A breakpoint-based silicon debug technique with cycle-granularity for handshake-based SOC,” IEEE Workshop of Register-Transfer and High Level Testing, pp. I.4.S, 2013.

  56. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and K. Chakrabarty, “A new LFSR reseeding scheme via internal response feedback,” IEEE Asian Test Symp. pp. 6B-3, 2013.

  57. W.-C. Lien and K.-J. Lee, “Output Bit Selection Methodology for Test Response Compaction,” IEEE Design Automation Conference, pp. 1-2 , 2013 (PhD Forum).

  58. K.-J. Lee, C.-Y. Chang, and H.-Y. Yang, “An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip,” IEEE Int’l VLSI Symp. on Design, Automation and Test., pp. DR61, 2013 (best paper award candidate).

  59. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and K. Chakrabarty, “A new selection algorithm to avoid unknown responses via counter-based output selection scheme,” VLSI Test Technology Workshop, pp. S4-1, 2013.

  60. W.-C. Lien, W.-L. Ang, T.-Y. Hsieh, and K.-J. Lee, “High-performance deterministic BIST using multiple twisted-ring counters,” VLSI DESIGN/CAD Symp., pp. S15-5, 2012.

  61. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty, and Y.-H. Wu, “Test response compaction based on a single counter,” VLSI Test Technology Workshop, pp. S3-1, 2012 (Best Paper Award).

  62. W.-C. Lien, K.-J. Lee, and T.-Y. Hsieh, “Output bit selection for test response compaction,” IEEE Int’l Conf. on Solid-State Integrated Circuit Technology (ICSICT), pp. S23_01, 2012.

  63. W.-C. Lien, K.-J. Lee, and T.-Y. Hsieh, “A Test-per-clock LFSR reseeding algorithm for concurrent reduction on test sequence length and test data volume,” IEEE Asian Test Symp. pp. 278-283, 2012.

  64. W.-C. Lien, T.-Y. Hsieh, K.-J. Lee, and K. Chakrabarty, “Accumulator-based output selection for test response compaction," IEEE Int’l Symp. on Circuits and Systems, pp. 2313-2316, 2012.

  65. W.-C. Lien, T.-Y. Hsieh and K.-J. Lee, “Routing-efficient implementation of an internal- response-based BIST architecture,” IEEE Int’l Symp. on Design, Automation and Test, pp. 1-4, 2012 (best paper nomination).

  66. K.-J. Lee, Alan Su, L.-F. Chen, J.-W. Jhou, J. Kuo, and M. Liu, “A software/hardware co-debug platform for multi-core systems” IEEE Int’l Conf. on ASIC (ASICON 11), pp. 2E-2, 2011.

  67. K.-J. Lee, C.-Y. Chang, and I.-J. Chen, “EPIDETOX: An ESL Platform for Integrated circuit DEsign and TOol eXploration,” IEEE Int’l Conf. on Hardware/Software Co-design and System Synthesis, pp. 381-384, 2011.

  68. A. Su, J. Kuo, K.-J. Lee, I.-J. Huang, G.-A. Jian, C.-A. Chien, J.-I. Guo, and C.-H. Chen, “Multi-core software/hardware co-debug platform with ARM CoreSight, on-chip test architecture and AXI/AHB bus monitor” IEEE Intl Symp. on VLSI Design, Automation and Test, pp. 1-6, 2011.

  69. W.-C. Lien, T.-Y. Hsieh, C.-T. Tsai, and K.-J. Lee, "A rotation-based BIST with self-feedback logic to achieve complete fault coverage," IEEE Int’l Symp. on VLSI Design, Automation and Test, pp. 252-255, 2011 (Best paper nomination).

  70. W.-C. Lien, K.-J. Lee, and T.-Y. Hsieh, “Concurrent determination of seeds and test sequences for LFSR reseeding,” VLSI Test Technology Workshop, pp. S2-1, Jul. 2011.

  71. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, and S.-S. Chien, “Test response compaction via accumulator-based output selection,” VLSI DESIGN/CAD Symp., pp. S4-3, Aug. 2011 (Best paper award).

  72. W.-C. Lien and K.-J. Lee, “A complete logic BIST technology with no storage requirement,” IEEE Asian Test Symp., pp.129-134, 2010.

  73. W.-C. Lien and K.-J. Lee, “Efficient mixed-mode BIST for complete fault coverage,” VLSI Test Technology Workshop, pp. S2-3, 2010.

  74. W.-C. Lien, Y.-T. Wang, Y.-H. Wu, and K.-J. Lee, “Counter-based output selection method for test response compaction,” Electronic Technology Symp. pp. BO-11, 2010.

  75. C.-Y. Chang, Y.-J. Chang, K.-J. Lee, J.-C. Yeh, S.-Y. Lin, and J.-L. Ma, “Design of on-chip bus with OCP interface,” IEEE Int’l Symp. on VLSI Design, Automation and Test, pp. 211-214, 2010.

  76. J.-W. Lin, C.-C. Wang, C.-Y. Chang, C.-H. Chen, and K.-J. Lee, “Full system simulation and verification framework,” IEEE Int’l Conf. on Information Assurance and Security, pp. 165-168, 2009.

  77. T.-Y. Hsieh, M.A. Breuer, M. Annavaram, S.K. Gupta, and K.-J. Lee, “Tolerance of performance degrading faults for effective yield improvement,” IEEE Int’l Test Conf., pp. 1-10, 2009.

  78. C.-Y. Chang, C.-Y. Hsiao, and K.-J. Lee, “Transaction level modeling and design space exploration for SOC test architectures,” IEEE Asian Test Symp. pp. 200-205, 2009.

  79. K.-J. Lee, C.Y. Chang, A. Su, and S.-Y. Liang, “A unified test and debug platform for SOC design,” IEEE Int’l ASIC Conf., pp. 577-580, 2009.

  80. C.-Y. Chang, Y.-J. Chang, K.-J. Lee, J.-C. Yeh, P.-J. Huang, and Y.-H. Chu, “Design of OCP wrappers and protocol converters for system integration,” VLSI Design/CAD Symp. pp. P1-22, 2009.

  81. T.Y. Hsieh, K.-J. Lee, and M. A. Breuer, “Test pattern generation for efficient identification of acceptable chips based on error-tolerance,” VLSI DESIGN/CAD Symp. pp. S18-1, 2009. (Best paper nomination)

  82. K.-J. Lee, S.-Y. Liang, and A. Su, “A low-cost soc debug platform based on on-chip test architectures,” IEEE Int’l SOC Conf. pp. 161-164, 2009.

  83. T.-Y. Hsieh, K.-J. Lee, and M. A. Breuer, “An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance,” IEEE Int’l Symp. on VLSI Design, Automation and Test, pp. 255-258, 2009.

  84. C.-M. Huang, C.-M. Wu, C.-C. Yang, K.-J. Lee, and C.-L. Wey, “Programmable system-on-chip (SoC) for silicon prototyping,” IEEE Int’l Symp. Industrial Electronics, pp. 1976~1981, 2008.

  85. L.-T. Wang, R. Apte, S. Wu, B. Sheu, K.-J. Lee, X. Wen, W.-B. Jone, C.-H. Yeh, W.-S. Wang, H.-J. Chao, and J. Guo, ” Turbo1500: toward core-based design for test and diagnosis using IEEE Std. 1500,” IEEE nt’l Test Conf., pp. 1-9, 2008.

  86. T.-H. Lu, C.-H. Chen, and K.-J. Lee, “A Hybrid software-based self-testing methodology for embedded processor,” ACM Symp. on Applied Computing (SAC), pp. 3378-3381, 2008.

  87. Y.-Y. Tsai, Y.-C. Lin, K.-J. Lee, C.-W. Yen, and C.-H. Chen, “A software-based test methodology for direct-mapped data cache,” IEEE Asian Test Symp. (ATS), pp. 363-368, 2008.

  88. C.-Y. Chang, K.-J. Lee, and J.-D. Wang, “Constructing on-chip test infra-structure at electronic system level, IEEE Workshop on RTL and High-Level Testing, pp. S1-4, 2008.

  89. C.-Y. Chang, K.-J. Lee, and J.-D. Wang, “On-chip test platform design at electronic system level,” VLSI DESIGN/CAD Symp., pp. S11-3, 2008.

  90. T.-H. Lu, C.-H. Chen, and K.-J. Lee, “A hybrid self-testing methodology of processor cores,” IEEE Int’l Symp. on Circuits & Systems (ISCAS), May 18-21, 2008.

  91. T.-Y. Hsieh, K.-J. Lee, C.-L. Lu, and M. A. Breuer, “A systematic methodology to employ error-tolerance for yield improvement,” IEEE Int’l Symp. on VLSI Design, Automation and Test, pp. 105-108, 2008.

  92. T.-Y. Hsieh, K.-J. Lee, and M. A. Breuer, “Chip quality grading to enhance effective yield,” VLSI Test Technology Workshop, pp. S1-5, 2008.

  93. K.-J. Lee, T.-Y. Hsieh, and M. A. Breuer, “Test pattern generation for a fault-oriented test methodology to improve yield based on error-tolerance,” VLSI Test Technology Workshop, pp. S1-1, 2007.

  94. T.-Y. Hsieh, K.-J. Lee, and J.-J. You, “Test efficiency analysis and improvement of SOC test platforms,” IEEE Asian Test Symp., pp.463-466, 2007.

  95. W.-C. Huang, C.-Y. Chang, and K.-J. Lee, “DASTEP: A design automation system for SOC test platform,” The 2nd Int’l PhD Student Workshop on SOC, 2007.

  96. W.-C. Huang, C.-Y. Chang, and K.-J. Lee, “Toward automatic synthesis of SOC test platforms,” IEEE Int’l Symp. on VLSI Design, Automation & Test (VLSI-DAT), pp. 156-159, 2007.

  97. T.-Y. Shieh, K.-J. Lee, and M.A. Breuer, “Reduction of detected acceptable faults for yield improvement via error-tolerance,” IEEE Design, Automation and Test in Europe (DATE), pp. 1599-1604, 2007.

  98. W.-C. Huang and K.-J. Lee, “DASTEP: A design automation system for system-on-chip test platform,” VLSI DESIGN/CAD Symp. pp. D3-5, 2006.

  99. C.-M. Huang, K.-J. Lee, C.-C. Yang, W.-H. Hu, S.-S. Wang, J.-B. Chen, C.-S. Chen, L.-D. Van, C. Wu, W.-C. Tsai, and J.-Y. Jou, “Multi-project system on-chip (MP-SoC): a novel test vehicle for SOC silicon prototyping,” IEEE Int’l SOC Conf., pp.137-140, 2006.

  100. T.-Y. Shieh, K.-J. Lee, and M.A. Breuer, “Maximizing yield improvement via error-tolerance by avoiding detection of acceptable faults,” VLSI DESIGN/CAD Symp. D3-3, 2006.

  101. T.-C. Huang, J.-C. Tzeng, Y.-W. Chao, J.-J. Chen, W.-T. Liu, and K.-J. Lee, “A supply-gating scheme for both data-retention and spike-reduction in power management and test scheduling,” IEEE Int’l Symp. on VLSI Design, Automation & Test, pp. 1-4, 2006.

  102. T.-Y. Shieh, K.-J. Lee, and M.A. Breuer, “An error-oriented test methodology to improve yield with error-tolerance,” IEEE VLSI Test Symp. pp. 130-135, 2006.

  103. K.-J. Lee, T.-Y. Shieh, and M.A. Breuer, “A novel test methodology based on error-rate to support error-tolerance,” IEEE Int’l Test Conf., Paper 44.3, pp. 1136-1144, 2005.

  104. S.-C. Shen, H.-M. Hsu, Y.-W. Chang, and K.-J. Lee, “High-speed built-in self-test for double data rate memory,” VLSI DESIGN/CAD Symp. pp. P2-65, 2005.

  105. T.-Y. Hsieh and K.-J. Lee, “Error-rate estimation for error-tolerance and yield improvement,” VLSI DESIGN/CAD Symp. 2005.

  106. W.-L. Wang and K.-J. Lee, “A complete memory address generator for scan based march algorithms,” IEEE Int’l Workshop on Memory Technology, Design& Test, pp. 83-88, 2005.

  107. S.-C. Shen, H.-M. Hsu, Y.-W. Chang, and K.-J. Lee, “A high-speed built-in self-test architecture for DDR SDRAM testing,” IEEE Int’l Workshop on Memory Technology, Design and Testing, pp. 52-57, 2005.

  108. K.-J. Lee, C.-Y. Chu, Y.-T. Hong, “An embedded processor based SOC test platform,” IEEE Int’l Symp. on Circuits and Systems, pp. 2983-2986, 2005.

  109. T.-P. Wang, C.-Y. Tsai, M.-D. Shieh and K.-J. Lee, “Efficient test scheduling for hierarchical core based design,” IEEE Int’l Symp. on VLSI Design, Automation, Test, pp. 200-203, 2005.

  110. C.-H. Huang, S.-J. Chang, and K.-J. Lee, “A 12-bit 40MS/s pipelined A/D converter using multiple-phase capacitor-splitting feedback interchange technique,” VLSI DESIGN/CAD Symp. pp. P2-13, 2004.

  111. M.-C. Chen, K.-J. Lee, and T.-L. Hsieh, “A Hybrid functional testing method for embedded processor cores,” VLSI DESIGN/CAD Symp. pp. A4-1, 2004.

  112. K.-J. Lee, Y.-C. Chiang, Y.-T. Hung, J.-H. Wang, and H.-P. Lin, “Advanced scan architecture for test time and test volume reductions,” VLSI DESIGN/CAD Symp., pp. A3-1, 2004.

  113. C.-H. Huang, S.-J. Chang, and K.-J. Lee, “Design of high-resolution pipelined analog-to-digital converters using multiple-phase capacitor-splitting feedback interchange technique,” IEEE Asian Pacific Conf. on Circuits and Systems, pp.625-628, 2004.

  114. S.-C. Shen, Y.-C. Lin, M.-D. Shieh, and K.-J. Lee, “Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits,” IEEE Asian Pacific Conf. on Circuits and System, pp. 178-180, 2004.

  115. C.-H. Huang, K.-J. Lee, and S.-J. Chang, “A low-cost diagnosis methodology for pipelined a/d converters,” IEEE Asian Test Symp. pp. 296-301, 2004.

  116. K.-J. Lee, S.-J. Hsu, and C.-M. Ho, “Test power reduction with multiple capture orders,” IEEE Asian Test Symp. pp. 26-31, 2004.

  117. K.-J. Lee, S.-J. Chang, and R.-S. Tzeng, “A sigma-delta modulation based BIST for A/D converters,” IEEE Asian Test Symp., pp. 124-127, 2003.

  118. K.-J. Lee, S.-J. Chang, and R.-S. Tzeng, “A sigma-delta modulation based BIST scheme for A/D converters,” VLSI DESIGN/CAD Symp. pp. 124-127, 2003.

  119. K.-J. Lee and J.-J. Chen, “Reducing test application time and power dissipation for scan-based testing via multiple clock disabling,” IEEE Asian Test Symp., pp. 338-343, 2002.

  120. J.-J. Chen and K.-J. Lee, “Test scheduling & clock disabling for test time and power reduction,” VLSI DESIGN/CAD Symp., pp. 456-459, 2002.

  121. Y.-T. Hung and K.-J. Lee, “An embedded-processor-driven platform for SOC testing,” VLSI DESIGN/CAD Symp., pp. 178-181, 2002.

  122. W.-L. Wang and K.-J. Lee, “A programmable data background generator for march-based memory testing,” IEEE Asia-Pacific Conference on ASIC, pp. 347-350, 2002.

  123. W.-L. Wang and K.-J. Lee, “Accelerated test pattern generators for mixed-mode BIST environments,” IEEE The 10th Anniversary Compendium of Papers from Asian Test Symp., pp. 335-340, 2001.

  124. K.-J. Lee, J.-J. Tang, T.-C. Huang, and C.-L. Tsai, “Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults,” IEEE The 10th Anniversary Compendium of Papers from Asian Test Symp., pp. 169-174, 2001.

  125. T.-C. Huang and K.-J. Lee, “A token structure for low power scan design,” IEEE Int’l Test Conf., pp. 660-669, 2001.

  126. T.-C. Huang and K.-J. Lee, “A low-power LFSR architecture,” IEEE Asian Test Symp. pp. 470, 2001.

  127. K.-J. Lee, J.-J. Chen and T.-C. Huang, “Test power reduction for scan-based design,” VLSI DESIGN/CAD Symp., pp. A3-10, 2001.

  128. W.-L. Wang and K.-J. Lee, “A universal and expandable data background generator for memory testing,” VLSI DESIGN/CAD Symp., pp. A3-7, 2001.

  129. T.-C. Huang and K.-J. Lee, “A token structure for low power scan design,” VLSI DESIGN/CAD Symp., pp. A3-1, 2001.

  130. K.-J. Lee and C.-I. Huang, “A hierarchical test control architecture for core based design,” IEEE Asian Test Symp. pp. 248-253, 2000.

  131. W.-L. Wang and K.-J. Lee, “Accelerated test pattern generators for mixed-mode BIST environments,” IEEE Asian Test Symp. pp. 368-373, 2000.

  132. K.-J. Lee, T.-C. Huang, and J.-J. Chen, “Test power reduction for multiple scan circuits during test application,” IEEE Asian Test Symp., pp. 453-458, 2000.

  133. Y.-C. Wen and K.-J. Lee, “Static parameters testing for A/D converters,” VLSI DESIGN/CAD Symp., pp. 417-420, 2000.

  134. T.-C. Huang and K.-J. Lee, “Interleaving multiple scan technique to reduce peak power,” VLSI DESIGN/CAD Symp. pp. 385-388, 2000.

  135. K.-J. Lee and C.-I. Huang, “A hierarchical test control architecture for core based design,” VLSI DESIGN/CAD Symp., pp. 227-230, 2000.

  136. Y.-C. Wen and K.-J. Lee, “An on-chip ADC test structure,” IEEE Design and Test Conf. of Europe (DATE), pp. 221-225, 2000.

  137. T.-C. Huang and K.-J. Lee, “An input control technique for power reduction in scan circuits during test application,” IEEE Asian Test Symp., pp. 315-319, Nov. 1999.

  138. S.-C. Chang, K.-J. Lee, Z.-Z. Wu and W.-B. Jone, “Test application time reduction by input signal sharing,” VLSI DESIGN/CAD Symp. pp. 115-118, Aug., 1999.

  139. W.-C. Wang and K.-J. Lee, “A systematic approach to design testable gm-C filters,” VLSI DESIGN/CAD Symp. pp. 183-186, 1999.

  140. T.-C. Huang and K.-J. Lee, “Test power reduction during scan operation via input control,” VLSI DESIGN/CAD Symp. pp. 107-110, 1999.

  141. K.-J. Lee, C.-Y. Hwang, and Y.-K. Tsao, “AFSPG: An automatic faulty SPICE program generation system,” VLSI DESIGN/CAD Symp. pp. 187-190, 1999.

  142. W.-L. Wang and K.-J. Lee, “A universal March pattern generator for testing embedded memory cores,” IEEE Int’l ASIC/SOC Conf. pp. 228-232, 1999.

  143. W.-L. Wang and K.-J. Lee, “An embedded March algorithm test pattern generator for memory testing,” IEEE Int’l Symp. on VLSI Technology, Systems, and Applications. pp. 211-214, 1999.

  144. K.-J. Lee, M.-C. Huang, and I.-H. Shih, “Functional test sequence generation and compaction for cache memory,” Microprocessor Workshop. pp. 90-93, 1999.

  145. W.-B. Jone, D.-C. Huang, S.-C. Wu, and K.-J. Lee, “A parallel testing method for embedded small buffers,” Microprocessor Workshop. pp. 83-89, 1999.

  146. K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Reducing test application time via input sharing,” Microprocessor Workshop. pp. 77-82, 1999.

  147. K.-J. Lee and W.-C. Wang, “A 0.5μm operational trans-conductance amplifier-capacitor filter with concurrent error detection capability,” IEEE Int'l Analog VLSI Workshop, pp. 103-108, 1999.

  148. W.-B. Jone, D.-S. Huang, and K.-J. Lee, “An efficient BIST method for small buffers,” IEEE VLSI Test Symp., pp. 246-251, 1999.

  149. K.-J. Lee, J.-J. Tang, W.-Y. Du, and T.-C. Huang, “On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation,” IEEE Asian Test Symp., pp.113-118, 1998.

  150. K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Using a single input to support multiple scan chains,” IEEE Int'l Conf. on Computer-Aided Design. pp. 74-78, 1998.

  151. K.-J. Lee, J.-J. Tang, W.-Y. Du, and T.-C. Huang, “On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation,” VLSI DESIGN/CAD Symp. pp. 173-176, 1998.

  152. K.-J. Lee, M.-C. Huang, and I.-H. Shih, “Functional testing for cache memory,” VLSI DESIGN/CAD Symp. pp. 165-168, 1998.

  153. T.-C. Huang and K.-J. Lee, “A new built-in current sensor for deep submicron CMOS ICs,” VLSI DESIGN/CAD Symp., pp. 141-144, 1998.

  154. K.-J. Lee and T.-C. Huang, “Bulk-driven technique for current testing,” IEEE Int'l Conf. on Chip Technology. pp. 158-165, 1998.

  155. T.-C. Huang and M.-C. Huang, K.-J. Lee, “Built-in current sensor designs based on the bulk-driven techniques,” IEEE Asian Test Symp. pp. 384-388, 1997.

  156. T.-C. Huang, M.-C. Huang, and K.-J. Lee, “A high-speed low-voltage built-in current sensor,” IEEE Int'l Workshop on IDDQ Testing, pp. 90-94, 1997.

  157. K.-J. Lee, T.-C. Huang, and M.-C. Huang, “A low-voltage built-in current sensing technique,” VLSI DESIGN/CAD Symp., pp. 51-54, 1997.

  158. C.-L. Lee, J.-Y. Jou, C.-S. Lin, J.-E. Chen, C.-W. Wu, K.-J. Lee, and C.-C. Su, “A joint project to develop a VLSI testing and design-for-testability course for universities in Taiwan,” IEEE Int’l Conf. on Engineering Education, pp. 43-53, 1997.

  159. K.-J. Lee, J.-J. Tang, T.-C. Huang, and C.-L. Tsai, “Combination of automatic test pattern generation and built-in intermediate voltage sensing for detecting CMOS bridging faults,” IEEE Asian Test Symp., pp. 100-105, Nov. 1996.

  160. K.-J. Lee and J.-J. Tang, “Two modeling techniques for CMOS circuits to enhance test generation and fault simulation for bridging faults,” IEEE Asian Test Symp., pp. 165-170, Nov. 1996.

  161. K.S. Huang and K.-J. Lee, “A current-mode testable and diagnosable design of OTA-C filters,” HD-Media Workshop, pp. A5-5/25-30, Nov. 1996.

  162. K.-J. Lee, J.-J. Tang, T.-C. Huang, and C.-L. Tsai, “Analysis of resistive inter-gate bridging faults In CMOS circuits,” VLSI DESIGN/CAD Symp., pp.73-76, Aug. 1996.

  163. T.-P. Lee, K.-J. Lee, and R.-C. Wen, “System level testing for mixed-mode circuits,” HD-Media Workshop, pp. PO1.14-PO1.19, Nov. 1995.

  164. J.-L. Kuo and K.-J. Lee, “A novel fault tolerant architecture for video filters,” HD-Media Workshop, pp. PO1.20-PO1.25, Nov. 1995.

  165. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “Analysis of resistive inter-gate bridging faults In CMOS circuits,” VLSI DESIGN/CAD Symp., pp.93-96, Aug. 1995.

  166. K.-J. Lee, J.-J. Tang, and C.-Y. Chen, “A simple and effective design of built-in intermediate voltage sensors,” VLSI DESIGN/CAD Symp., pp.43-46, Aug. 1995.

  167. K.-J. Lee, J.-J. Tang, and K.-S. Huang, “A built-in current sensor based on current-mode and dual-power design,” VLSI DESIGN/CAD Symp., pp.26-29, Aug. 1995.

  168. K.-J. Lee, S.-Y. Jeng, and T.-P. Lee, “A new architecture for analog boundary scan,” IEEE Int'l Symp. on Circuits and Systems, pp. 409-412, May 1995.

  169. J.-J. Tang, B.-D. Liu and K.-J. Lee, “An IDDQ fault model to facilitate the design of built-in current sensors (BICSs),” IEEE Int'l Symp. on Circuits and Systems, pp. 393-396, May 1995.

  170. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “Built-in intermediate voltage testing for CMOS circuits,” IEEE European Design and Test Conf., pp. 372-376, Mar. 1995.

  171. C.-H. Kuo and K.-J. Lee, “Concurrent error detection, diagnosis and fault tolerance for operational trans-conductance amplifier capacitor based video filters,” HD-Media Workshop, pp.PO2.1-PO2.6, Oct. 1994. (Best paper award)

  172. K.-J. Lee, J.-J. Tang, and B.-D. Liu, “Built-in intermediate voltage testing for CMOS circuits,” VLSI DESIGN/CAD Symp., pp.245-250, Aug. 1994.

  173. K.-J. Lee and C.-H. Kuo, “Concurrent error detection, diagnosis and fault tolerance for switched-capacitor filters,” VLSI DESIGN/CAD Symp., pp.205-210, Aug. 1994.

  174. K.-J. Lee, M.-H. Lu, and J.-F. Wang, “A systematic method to classify scan cells,” IEEE Asian Test Symp., pp.219-224, Nov. 1993.

  175. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A new representation for programmable logic arrays to facilitate testing and logic design,” IEEE TENCON'93, pp.561-564, Oct. 1993.

  176. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A real time IDDQ testing scheme using current conveyor technique,” Int'l Symp. on IC Technology, Systems & Applications, pp.348-352, Sep. 1993.

  177. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “Maximum fault diagnosis resolution for programmable logic array,” Int'l Symp. on IC Technology, Systems & Applications, pp.100-104, Sep. 1993.

  178. J.-J. Tang, K.-J. Lee, and B.-D. Liu, “A new current sensing technique for IDDQ testing,” VLSI DESIGN/CAD Workshop, pp.166-170, Aug. 1993.

  179. W.-L. Wang, K.-J. Lee, and J.-F. Wang, “Design of real time fault detectors using linear feedback shift registers,” IEEE Int'l Electron Devices & Material Symp., pp.193-195, Nov. 1992.

  180. W.-L. Wang, J.-F. Wang, and K.-J. Lee, “A fast testing method for sequential circuits at the state transition level,” IEEE Int'l Test Conf., pp. 514-519, Sep. 1992.

  181. K.-J. Lee, C.A. Njinda, and M.A. Breuer, “SWiTEST: A switch level test generation system for CMOS combinational circuits,” IEEE Design Automation Conf., pp. 26-29, Jun. 1992.

  182. K.-J. Lee and M.A. Breuer, “Constraints for using IDDQ testing to detect CMOS bridging faults,” IEEE VLSI Test Symp., pp. 303-308, May 1991.

  183. K.-J. Lee and M.A. Breuer, “A new method for assigning signal flow directions to MOS transistors” IEEE Int'l Conf. on Computer-Aided Design, pp. 492-495, Nov. 1990.

  184. K.-J. Lee and M.A. Breuer, “On the charge sharing problem in CMOS stuck-open fault testing,” IEEE Int’l Test Conf., pp. 417-426, Sep. 1990.

  185. K.-J. Lee and M.A. Breuer, “On detecting single and multiple bridging faults In CMOS circuits using the current supply monitoring method,” IEEE Int’l Symp. on Circuits and Systems, pp. 5-8, May 1990.

  186. K.-J. Lee and M.A. Breuer, “A universal test sequence for CMOS scan registers,” IEEE Custom Integrated Circuit Conf., pp. 28.5.1-28.5.4, May 1990.

  187. M.A. Breuer, R. Gupta, R. Gupta, K.-J. Lee, and J.C. Lien, “Knowledge-based systems for test and diagnosis,” IIFIP Workshop on KBS for Test & Diagnosis, Grenoble, France, pp. 3-28, Sep. 1988.


C.    Patents (Publications Top Page)

  1. 李昆忠,陳郁翔,”具掃描鍊架構與邏輯單元矩陣之測試晶片架構及其診斷方法” ROC Invention patent no. I734420, July 21, 2021.

  2. 李昆忠,吳家騏,郭蔓萱,”測試電路之動態密鑰防禦架構與方法” ROC Invention patent no. I725900, May 11, 2021.

  3. K.-J. Lee, J.-Z. Chen, “Test Decompressor and Test Method Thereof,” 10,324,130,Jun.18, 2019, USA.

  4. K.-J. Lee, P.-H. Tang, “Integrated Circuit Automatic Test System and Integrated Circuit Automatic Test Method Storing Test Data in Scan Chains,” 10,324,129, Jnu. 18, 2019, US.

  5. K.-J. Lee, J.-Z. Chen, 一種測試資料之解壓縮器及其測試方法, I612317, 2018/1/21, ROC.

  6. K.-J. Lee, C.-H. Wu, W.-C. Lien, H Lin, Y Liu, J Chen, Defect Diagnosis, invention patent number 9,766,286, 2017/9/19, USA.

  7. K.-J. Lee, P.-H. Tang, An on-chip self-test architecture with test patterns recorded in scan chains, I609190, 2017/12/21, ROC.

  8. S. J. Chang, G.-Y. Huang, K.-J. Lee, W.-Y. Su, C.-H. Chen, L.-Y. Chiou, C.-H. Kuo, C.-H. Tsai, and C.-M. Lin, “Multi-point temperature sensing method for integrated circuit chips and system of the same,” invention patent number 9,448,122, 2016/9/20, USA.

  9. K.-J. Lee, and L.-J. Lee, “Three-dimensional IC test system and its method,” invention patent number 1530701, 2016/4/20, ROC.

  10. S. J. Chang, G.-Y. Huang, K.-J. Lee, W.-Y. Su, C.-H. Chen, L.-Y. Chiou, C.-H. Kuo, C.-H. Tsai, and C.-M. Lin, “Method for sensing multi-point temperatures applied to integrated circuit chips and system for the same,” invention patent number I489093, 2015/6/21, ROC.

  11. K.-J. Lee, and Jia-Wei Jhou, “Debugging control system using inside-core event as trigger condition and method of the same,” invention patent number I472912, 2015/2/11, ROC.

  12. K.-J. Lee, and Jia-Wei Jhou, “Debugging control system using inside-core event as trigger condition and method of the same,” invention patent number 8,892,973, 2014/3/13, USA.

  13. C.-M. Huang, C.-C. Yang, J.-Y. Jou, K.-J. Lee, and L.-D. Van, “Multiple-Project System-On-Chip and its Method,” invention patent number 306211, 2009/02/11, Taiwan, ROC.

  14. C.-M. Huang, C.-C. Yang, J.-Y. Jou, K.-J. Lee, and L.-D. Van, “Multiple-Project System-On-Chip and its Method,” invention patent number 7,571,414, 2009/08/04, USA.

  15. K.-J. Lee, J.-J. Chen and C.-H. Huang, “Test method and architecture for circuits having inputs,” invention patent number 7159161, 2007/01/02, USA.

  16. K.-J. Lee, J.-Y. Wu and W.-B. Jone, “Built-in Self-Test for Multiple Memories in a Chip,” invention patent number 6,360,342, 2002/03/19, USA.

  17. K.-J. Lee, T.-P. Lee and S.-Y. Cheng, “An analog boundary scan design,” invention patent number 125758, 200012/01, Taiwan, ROC.

  18. K.-J. Lee, J.-Y. Wu and W.-B. Jone, “Built-in Self-Test for Multiple Memories in a Chip,” invention patent number 123572, 2000/11/11, Taiwan, ROC.

  19. K.-J. Lee, J.-J. Chen and C.-H. Huang, “Test architecture and test generation method for using one data input to support multiple scan chains,” invention patent number 118268, 2000/07/21, Taiwan, ROC.

  20. K.-J. Lee and J.-J. Tang, “A built-in current sensor based on current mode technique,” invention patent number 111969, 2000/02/11, Taiwan, ROC.

  21. K.-J. Lee and J.-J. Tang, “Built-in current sensor for IDDQ monitoring,” invention patent number 5,808,476, 1998/09/15, USA.

  22. K.-J. Lee and J.-J. Tang, “Intermediate voltage sensor for CMOS circuits,” invention patent number 5,631,575, 1997/05/20, USA.

  23. K.-J. Lee and J.-J. Tang, “Intermediate voltage sensors for CMOS circuits,” invention patent number 077093, 1996/02/11, Taiwan, ROC.

  1. Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba,
    VLSI TEST PRINCIPLES AND ARCHITECTURES,
    Ch6 Test Compression(p341-p396), MORGAN KAUFMANN,
    2006,
      ISBN:978-0-12-370597-6

  2. K.J. Lee. Switch level test generation for CMOS circuits. PhD Dissertation, Univ. of Southern California, Los Angeles, August 1991.  

 

Books:

  1. Innovation 2007, Chapter 36: A Novel Cost-Efficient Silicon Prototyping Service for Academic SoC Designs, First author, International Network for Engineering Education and Research (iNEER), 2007.

  2. SOC Design Overview, Chapter 8: SOC Testing. (Single author for the chapter), McGraw Hill, 2006.

  3. VLSI Test Principles and Architectures, Chapter 10: Boundary Scan and Core-Based Testing. (Single author for the chapter), Elsevier, 2006.

  4. VLSI Test Principles and Architectures, Chapter 6: Test Compress, Coauthoring with XianWey Li and Bur Touba, Elsevier, 2006.

    

 

 

 

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