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負責人
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| 研究／教學專長 |
Communication
/ Analog / Digital IC design |
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簡介
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The motivation for networks is
the need to share data resources. Central data files are costly
to duplicate and expensive to maintain. It is often expedient
to maintain central files or data banks that are shared by other
devices at workstations throughout a network.
To implement such a network function, one has to design a network
processor by employing advanced ASIC technology with serial
link interface to reduce costs. On the other hand, ASIC vendors
and foundries will implement the macrocells and add them to
their device libraries. Thus the time and risk can be minimized.
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上課大綱
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- Introduction
- Data communication protocol
- Serial link architecture
- Data recovery algorithms
- Interface circuits
- Conclusion
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實習大綱
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- System architecture
- Circuit design - DPLL for data recovery
- Verilog HDL coding and simulation
- Testability and fault coverage
- Verification with FPGA
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預期成果
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The goal for the network device shall be
easy maintained with the characteristics of
- Fault coverage over 99%
- Data rate over 100Mbps
- The design shall be easily re-synthesized
with different technologies
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