負責人
姓名 許明華 學校/系所/職稱 雲林科技大學/電子工程/副教授
電話 05-5342601 Ext.4320 電子信箱 sheumh@cad.el.yuntech.edu.tw
研究/教學專長 VLSI/CAD Design, Algorithm Analysis, Digital Signal Process
簡介

The world of digital design is changing quickly. At a breathtaking rate, devices are becoming faster, smaller, and denser. Now there are programmable devices with million gates in tiny packages. It is possible for mainstream designer to design a prototyping system or create a digital IP on FPGA. Therefore, the purposes of this chapter are :

  • Master the synthesizable HDL and optimization techniques for FPGA implementation
  • Keep up with the changing digital technology and design prototyping systems for various applications
上課大綱
  • FPGA Design Strategies and Techniques
  • Synthesizable HDL Design and Optimization Techniques
  • Managing complexity-Large Designs
  • Improving Timing, Area and Power
  • Synthesis to FPGA
  • Mixed Technology Design
  • Reuse Strategies and Tasks
  • Prototype Design for Digital Signal Processing or Communications or processors & I/O peripheral
實習大綱
  • HDL design for the specific hardware architecture
  • Simulation and verification for HDL Design
  • FPGA optimization synthesis
  • Prototyping implementation
  • Test and Measurement
預期成果
  • 上年度之成果 (summary)
    • 上課教材完成
    • 上機操作影片製作
    • 開授DIP設計概論課程(91學年度第一學期)
  • 本年度之工作目標
    • 上課教材增修
    • DIP設計實例完成